Transistor frequency standard



Aug. 23,1960 J. H. SMITH EIAL TRANSISTOR FREQUENCY STANDARD Filed Aug. 31, 1955 INVENTORS Jar/7. 5mm Mae/n5. CAM/ 5514 BY Mia; z lfifi/my ATTORNEYS I Patented Aug. 23, 1960 'rRAusrsroR FREQUENCY STANDARD Joe H. Smith and Mark S. Campbell, Dallas, Tern, assigners to Texas Instruments Incorporated, Dallas, Ten, a corporation of Delaware Filed Aug. '31, 1955, Ser. No. 531,719

2 Claims. (Cl. 331-37) This invention relates to standard frequency generators and more particularly to a transistor oscillator circuit producing accurate low frequency pulses for precision timing of a sequence of events.

Many modern scientific investigation procedures re-- quire precise timing of various phenomena. One such investigation procedure is the commonly used seismic method of oil exploration. In this method, the subsurface structure of the earth is determined by creating a disturbance in the earth, usually by a subsurface explosion and detecting, at several accurately known locations, the shock waves produced by the disturbance. The detected shock waves are then transmitted, as electrical signals, to a central location where they are recorded in a side-byside relationship on the same record for purposes of comparison. For the accurate interpretation of these records, it is essential that precise timing indications be marked on the record. Accuracy to one part in ten thousand is the usual requisite for such timing lines. Because it has been found economically unfeasible to manufacture, in the quantities needed, crystal or tuning fork controlled timing line generators which are capable of such accuracy through several years of hard use in the field, the usual practice is to compromise between cost and accuracydependability in the design and manufacture of such devices. Consequently, it has been necessary to subject timing generators in field use to periodic accuracy tests by comparison with an extremely accurate and stable standard frequency generator.

One such standard frequency generator generally in use at the present time is a reasonably small tuning fork controlled unit operating from 110 volt, 60 cycle power. These standard units are usually tested for accuracy at some centralized laboratory location and then sent to a field operation to be used in a comparison test with the particular timing line generator used in that field operation. The standard generator is then returned to the laboratory where it is again tested to determine if its accuracy had been impaired in transit. The standard is next shipped to another field installation for comparison tests of the timing line generator at that installation.

The transistor frequency standard of the present invention is a portable, low voltage, battery operated unit using a crystal controlled oscillator and transistor divided circuits to achieve a low frequency output signal of the accuracy required.

It is one object of the present invention to provide a standard frequency oscillator which is accurate to one part in ten thousand when operating in ambient temperatures over the range of from 40 F. to +140 F.

It is another object of the present invention to provide a standard frequency oscillator for testing the accuracy of timing indication generators which has a much better long-time stability and is much smaller than presently used portable frequency standards.

It is still another object of the present invention to provide a small, light-weight, battery operated frequency standard which is less susceptible to inaccuracies due to dough handling and abusive treatment than other portable frequency standards presently available.

It is a further object of the present invention to provide a portable frequency standard device which is much smaller and less expensive than presently available frequency standards of comparable accuracy.

Other objects and advantages of the frequency standard of the present invention will become apparent from the following detailed description when read in conjunction with the accompanying drawing in which the single figure is a schematic diagram depicting the preferred embodiment of the electrical circuitry for the standard frequency generator of the present invention.

Referring now to the drawing, the dashed-line section of the diagram designated generally by the numeral 1 is the primary frequency oscillator section of the standard frequency generator. The primary frequency of the device is set and governed by the natural frequency of the crystal 2. In the preferred embodiment illustrated, the crystal 2 is a low activity crystal exhibiting high Q, high series resonant resistance and frequency deviation of i0.010% over a temperature range of -40 C. to +70 C. when operating at a frequency of eight kilocycles per second. Such a crystal is the type 3-] audio frequency crystal manufactured by the Hill Electronic Engineering and Manufacturing Company, Incorporated of New Kingston, Pennsylvania. It will be appreciated that the invention herein described is by no means limited to the use of the above mentioned crystal but that other suitable types may equally well be used to perform the same function.

In the oscillator circuit, the crystal has one terminal connected through the resistor 3 to ground and also through the coupling capacitor 4 to the base of the transistor 5. The base of the transistor 5 is connected through the bias resistor 6 to B+ voltage and its collector is tied directly to B+ voltage. The emitter of transistor 5 is connected to B voltage through the resistors 7 and 8. The grounded base transistor 10 has its collector connected to B+ voltage through the resistor 9 and is coupled to the output of transistor 5 by the connection of its emitter to the resistor 8. Thus, when power is applied to the circuit, the initial pulse causes the crystal 2 to begin oscillation. The oscillation signal from the crystal is fed through the transistor 5- and coupled to the transistor 10 through their common resistor 8. The signal current is amplified, without phase reversal, by the transistor 10 and applied through the coupling capacitor 11 to the crystal to sustain oscillations of the crystal. Both transistors of the circuit are considerably overdriven with the result that the output from the collector of the transistor 10 is essentially a square-wave and the output power is much in excess of that needed to sustain oscillations of the crystal. Thus, a useful output signal can also be taken from the collector of transistor 10 and fed through line 12 to the pulse amplifier designated generally as 13.

The square-Wave output signal from the oscillator section 1 is fed through the coupling capacitor 14 to the base of the grounded emitter transistor 15 in the pulse ampliher 13. The collector of the transistor 15 is connected to B+ voltage through the resistor 16 and its base is connected through the bias resistor 17 to B+ voltage. The coupling capacitor 14 and the resistor 17 also act as a net- 5 work to differentiate the square-wave signal from the oscillator section 1 so that the actual signal on the base of transistor 15 is a series of sharp pulses at the oscillator frequency. As stated above, for the specific embodiment of the present invention here illustrated, this frequency is eight kilocycles per second. These pulses are amplified and inverted by transistor 15 and fed through the coupling a in the transistor occurs.

. 3 capacitor 18 to the base of transistor 19. The collector of transistorr19 is tied directly to 13+ voltage. The load resistor 21 of the transistor'19 is connected between the emitter and. ground. Thiscircuit, which is the transistor equivalent. of. the vacuum-tube cathode follower circuit well-known in the electronics art, isused as the drlver'supthrough the capacitor .25 to the emitter of transistor 19 from'whichit receives its input, signal. The base of transistor 23 is connected to ground through the resonant circuit comprised of the inductance 26 and the capacitor 27. The collector of transistor 23 is connected to B- voltage through the resistor 28 and is coupled to ground through the capacitor 29. Again with reference only to the'particular, embodiment shown, it is desired that this circuit divide the frequency of the input pulse by four. To

' achieve thisresult, the circuits of the collector and case are both tuned to the desired output frequency.

1 The tuning of the collector is accomplished by choosing 'the'values of the resistance 28 and. the capacitance 29 such that their-time constant is slightly greater than the period of the desired output frequency, which for this divider is one-fourth the input frequency or two kilocycles. By this means, there is produced on the collector an exponentially increasing negative bias voltage approaching, at its peak, the value of collector bias voltage at which the transistor will exhibit a negative resistance between its base and collector. Because of the selected time constant of resistor 28 and capacitor 29, every fourth input pulse on the emitter occurs when the collector bias is somewhere near its peak. This input pulse on the emitter, occurring at a time when the collector bias voltage has driven the transistor toward its negative resistance region,

7 will drive the transistor sharply into the negative resistance region. The capacitor 29 will then quickly discharge through. the collector to base negative resistance of the transistor and the collector bias will be reduced to a height will appear at the amplifier 33 input. This variation will also appear at the input and the output of both drivers 38 and 39 since they are both fed from the amplifier circuit 33. Such variation may cause unreliable frequency division by the dividers. 36 and 37. Therefore, diode clippers 44 and 45 have been placed across the inputs of the two dividers to limit and equalize the pulse height. The drivers and 41 have their collectors connected to the source of 13+ voltage and their emitters connected to ground through their respective load resistors 46 and 47. e The action ofthe drivers 38 and 39 is identical to that of the previously di'scussed driver'circuit of transistor 19 and therefore, no further explanation is believed necessary. j

The transistor 54 of the divider 36receives input pulses on its enutter through the capacitor 48 at the output frequency of divider 2 2, that is, two thousand cycles per second i-n'the illustrated embodiment. With the emitter of transistor 54 connected to ground through the variable resistance 49, the base connected to ground through the resonant circuit comprised of inductance 50 and capacitance 51 and the collector tied to B'- voltage through resistor 52 and coupled to ground'through capacitor 53, the circuit of divider 36 is exactly the same as that of the divider 22 with the exception that the resistor 49-15mm variable in order that slight bias adjustments can be made to allow the interchangeable use of transistors having.

slightly different characteristics. This variable bias was found desirable to improve the stability of the circuit when operating at frequencies as low as required of the divider 36. In'the illustrated embodiment, the divider 36 produces at its output pulses at one' fourth the frequency of the received pulses or five hundred cycles per second through action identical to the action of the divider 22. These output pulses taken from the collector of transistor 54, are fed to the mixer circuit 55 through the coupling capacitor 56. v 1 Y As stated above, the driver 39 for the divider 37 receives pulses from the samesource, amplifier 33, as does the driver 38 for the divider 36. The divider '37, however,

' divides these pulsesby'five instead of four.v It is basically value well below the point at which negative resistance When the transistor is driven out of its negative resistance region, the capacitor 29 again recharges through the resistor 28 and the action is repeated .Two cycles *of. thiscollector circuit voltage waveform are shownat 31. e

In the base circuit, the inductance 26' and the capacie tance27 form'a tank circuit resonant at thedesired output frequency and producing a sine wave of voltage on a the base of transistor '23. The basecircuit receives'its energy from the pulse produced when the collector capacitor 29 is discharged and will oscillate .with its negative peak voltage coinciding with every *fourth positive pulse on the emitter; Since a negativevoltageonthe base of the 'transistor' has the 'same effect as a positive'voltage on the same circuit as the divider 36 but has incorporated in it an additional feature to provide even greater stabilityat its operating frequency which'is lower than that of either divider 36 or divider 22. As in the dividers 22 'and 36,

the base of the transistor 57 in the divider 37 is connected 7 a to ground through a circuit, comprised of the inductance 58 and thecapacitance 59 resonant at the desired output frequency. The collector of transistor 57 is coupled to ground through the capacitor 6fl and, to B-'Evoltage I through the resistor 61.- The values of resistance, 61 and the emitter, the eifcct of the coincident occurrenceof the positive peak on the emitter and the negative peak on the .base is to produce a very positive trigger action to drive the transistor into its negative resistanceiregion'thusproviding an extremely high degree of stability in thegdivideiz. V The output pulses from the divider 22 are fed through couplingcapacitor 3210 the base ofthe pulse amplifier 33, transistor 34, which .has its-emitter grounded and its co-llector connected to'B-l voltage through'the load resistor capacitance 6G arechosen such that their time constant is 1 approximately equal to the period of thedesiredfrequency output. V

'The signal from the emitter of transistor 41 is fed to the emitter of transistor 57 through the coupling capacitor 62. Also-connected to the emitter of transistor 57 is a charging and bias circuit comprised ofresistance63, resistance 64 and capacitance 65. Self-bias is applied to the transistor 57 emitter by the series connection of resistances 63 and 64 between the emitter and groundgIn order to provide the temperature stability necessary in this low '35. Theamplified pulses from the collectorof transistor 34 are-thenfedtotwodiwider circuits 36-and 37 simul- .taneously through=their respective driver circuits 38 and; .39. These, two driver circuits are identical andboth receive-the input pulse fromthe amplifier 33,011 the base of their transis'tors 40and 41 through the coupling capaci- 'Jtors42'and 43 respectively; Because the divider 22 presents'a radicallyidifierentloadto the grounded emitter.

pulseamplifie'rfiS when it switcheslavariation in pulse frequency circuit, resistance 63 is aresistor having ahigh negative temperature coefficient of resistance fSuchresistors are commonly called 'thermistofsand are .well-known in the electronics art. 7 Unlike ;most..ordinary resistors fvvhose resistanceincreases with an increase in temperature, thermistors exhibit a decreaseip resistancewith an increase in temperature. Thus, the changes in the internal equivalent resistances of. the transistor 57' due to changes in the ambient temperature are compensated for by changes in 'thebias current efiected by theEinversechange' in resistance of the thermistor'with' the ambientztemperature change. To provide even greater stability andallow useof transistor types having a fairly' wide range of characteristics in this circuit, the resistor 64, like the resistor 4-9 of the divider 36, is made variable.

combina ion of resistance 64 and capacitor 65 uit which acts in much the same circuit of resistor =61 and capacicllector circuit of transistor 57. As the "t produces a slow exponential ine the emitter of transistor 'duced by capacitance 50 and refince 61 drives the transistor very close to its negacc region. The values of resistance 64 and w are chosen such that the time constant is just slightly greater than the period of the desired output frequency, which for this particular rour h nced cycles per second. Thus, with the incoming pulses from the divider 22 superimuosed on the saw-tooth voltage generated by the charging circuit, every fifth pulse will drive the transistor into -ough emitter-to-base negative re- 's or. Two cycles of this voltage n on the fill'lilllel of transistor 57 are illustrated tency of the output pulse from the collector of transistor 5'7 is then one-fifth the frequency of the in ut pulses. These output pulses are fed through the capacitor 67 to the same mixer circuit 55 also recc'vrng be output pulses from divider 36 through the capacitor e mix I cir cide ce mixer.

is of the type known as a coinse of the mixer transistor as is l voltage through the resistor '39. The transistor is biased below cutoff by conection of its emitter to B- voltage through the resistors 70 and 71. The exact bias potential required will de pend upon the amplitude of the incoming pulses from the dividers 36 and 37 because the bias potential must be such that the pulses from either divider 36 or 37 alone will not drive the transistor into its conductive region but coincident occurrence of both pulses will cause the transistor to conduct. Thus, for the embodiment used herein for illustration, with input pulses from divider 36 at a frequency or" five hundred cycles per second and input pulses from divider 37 at a frequency of four hundred cycles per second, the pulses on the emitter of transistor 68 are coincident at their difference frequency or one hundred cycles per second and the output of the circuit Will be pulses at that frequency. In order for the bias on the emitter of transistor 68 to remain such that the transistor will not conduct unless the two incoming pulses occur simultaneously over a wide range of temperatures the bias resistor 71, like resistor 63, is a thermistor having a high negative thermal coefiicient of resistance.

Through such a mixer circuit, the use of a divider circuit of the same type as dividers 22, 36, and 37 to obtain the desired output frequencies can be avoided. Such divider circuits are undesirable for use at this point in the system because they are extremely unstable at low frequencies and especially at frequencies below two hundred and fifty cycles per second.

The final stage of the standard frequency generator is the output circuit 72 consisting of the transistor 73, the capacitor 74 and the resistor 75. Signal pulses from the mixer 55 are fed through the coupling capacitor 74 to the base of the transistor 73 which has its collector connected directly to B+ voltage and its emitter connected to ground through the load resistor 75. This circuit is the transistor equivalent of the vacuum-tube cathode follower circuit and is now well-known in the electronics art. It is quite often used as an impedance matching output c rcuit. The standard frequency output signal, which is at a frequency of one hundred cycles per second for the particular embodiment described,

is taken across the load resistor 75' of the final stage 72 at the terminals 76.

Thus, there has been described a standard frequency generator capable of produ ing an output frequency accurate to one part in ten thousand over an operating temperature range or" from '4G F. to +l40 P. which has the advantages of being portable, compact, batteryopcratcd and relatively inexpensive.

Although only the preferred embodiment has been illustrated, many changes, substi trons, and alterations still Within the spirit and scope of the standard frequency generator of the present in ention Will be apparent to those skilled in the art. it is therefore intended that this invention be limited only as set forth in the appended claims.

What is claimed is:

1. A transistorized standard low frequency generator comprising an oscillator stage, a first divider stage receiving signals from said oscillator stage and producing signals of a sub-multiple frequency of said received si nals, a second divider stage receiving signals from said rst divider stage and producing signals of a sub-multiple frequency of the signals from said first divider stage, a third divider stage receiving signals from said first divider stage and producing signals of a submultiple frequency of the signals received from said first divider stage and different from the frequency of the signals produced by said second divider stage, and a coincidence mixer stage receiving signals from said second divider stage and said third divider stage and producing only a signal of a frequency equal to the difference between the frequency of the signals from the said second divider stage and the frequency of the signals from said third divider stage.

2. A transistorized standard low frequency generator comprising an oscillator stage, a first-amplifier stage receiving and amplifying signals from said oscillator stage, a first driver stage receiving said amplifier signals, a first divider stage receiving signals from said first driver stage and producing signals at a sub-multiple frequency of said received signals, a second amplifier stage receiving and amplifying signals from said first divider stage, a second driver stage receiving signals from said second amplifier stage, a second divider stage receiving signals from said second driver stage and producing signals at a sub-multiple frequency of the signals from said first divider stage, a third driver stage arranged to receive signals from said second amplifier stage, a third divider stage receiving signals from said third driver stage and producing signals of a sub-multiple frequency of the signals from said first divider stage and different from the frequency of the signals produced by said second divider stage, a coincidence mixer stage receiving signals from said second and third divider stages and producing only a signal of a frequency equal to the difference between the frequency of the signals produced by the said second divider stage and the frequency of the signals produced by said third divider stage, and an output stage receiving the signals from said coincidence mixer stage and applying said received signals to output terminals.

References Cited in the file of this patent UNITED STATES PATENTS 

